Zybo Z7-20 ADI I2S Module Customization Memorandum

This is the Device ADI I2S IP module customizing (Vivado) part of the Zybo Z7-20 audio system project. Appreciated Yuhei Horibe’s literature for Zedboard I2S implementation and many of the Q&A for Zybo+I2S+PL300 DMA on “ADI Engineer Zone”.

The tool environments and preparation

Before starting this project, I have confirmed a LINUX boot on the Zybo Z7-20 Rev. B board with following the tool environments as an initial preparation.

OS: Ubuntu 18.04 LTS on VirtualMachine in MacBook
HW: Xilinx Vivado/Vitis 2020.2
SW: Petalinux 2020.2

Confirm the Audio-out on the Zybo platform

Build LINUX and have confirmed “Login” through /dev/ttyUSB1, and the kernel has recognized I2S Tx/Rx and SSM2602 device-driver, then got audio-out, see the last memorandum.

Change to handle 32bit I2S format

ADI axi_i2s_adi default mode is 24 bit as maximum data width, yet we would like to handle 32bit wide for the project. Need to modify both module config and “axi_i2s_adi.vhd” source.

Change to 32 for Slot Width

Edit <project>.gen/sources_1/bd/design_1/ipshared/c050/axi_i2s_adi.vhd

Since internal FIFO was 24bit hard corded and not reflect SLOT_WIDTH, IP configuration parameters.

% diff -p axi_i2s_adi.vhd axi_i2s_adi.vhd.orig 
190c190
< signal rx_sample			: std_logic_vector(31 downto 0);
---
> signal rx_sample			: std_logic_vector(23 downto 0);
220c220
< 				FIFO_DWIDTH => 32
---
> 				FIFO_DWIDTH => 24
230c230
< 				s_axis_tdata => s_axis_tdata(31 downto 0),
---
> 				s_axis_tdata => s_axis_tdata(31 downto 8),
248c248
< 				FIFO_DWIDTH => 32
---
> 				FIFO_DWIDTH => 24
264c264
< 				m_axis_tdata => m_axis_tdata(31 downto 0),
---
> 				m_axis_tdata => m_axis_tdata(31 downto 8),
288c288
< 				FIFO_DWIDTH => 32,
---
> 				FIFO_DWIDTH => 24,
297c297
< 				in_data => wr_data(31 downto 0),
---
> 				in_data => wr_data(31 downto 8),
329c329
< 				FIFO_DWIDTH => 32,
---
> 				FIFO_DWIDTH => 24,
451c451
< 			when 10 => rd_data <= rx_sample;
---
> 			when 10 => rd_data <= rx_sample & std_logic_vector(to_unsigned(cnt, 8));

XSA file generation

Then generate “<file name>.xsa” file for Petalinux by “File” -> “Export” -> “Export Hardware” and should click the “include bitstream” button.

Copy bit file to image/linux/system.bit

Since it is only internal circuit modification in the I2S module of FPGA, there is no need to rebuild the LINUX kernel, then need to pack “HW.bit” file into BOOT.BIN.

% petalinux-config --get-hw-description ../project_1/<project>.xsa
% cp project-spec/hw-description/design_1_wrapper.bit image/linux/system.bit
% petalinux-package --boot --force --fsbl images/linux/zynq_fsbl.elf --fpga images/linux/system.bit --u-boot

Copy image and rootfs to SD-card

% cd images/linux
% sudo cp BOOT.BIN boot.scr image.ub /media/sdcard/boot/
% sudo tar xf rootfs.tar.gz -C /media/sdcard/root/
% sudo sync

Boot LINUX and login

% speaker-test -t sine -F S32_LE

Check I2S signal by Oscilloscope.

Confirmed 32bit wide data on I2S DATA out.

Reference Link

Problems with audio driver in Petalinux