Zybo Z7-20 Audio Hardware Design Memorandum
This is the Hardware Designing (Vivado) part of the Zybo Z7-20 audio system project. Appreciated Yuhei Horibe's literature for Zedboard I2S implementation and many of the Q&A for Zybo+I2S+PL300 DMA on “ADI Engineer Zone”.
The tool environments and preparation
Before starting this project, I have confirmed a LINUX boot on the Zybo Z7-20 Rev. B board with following the tool environments as an initial preparation.
OS: Ubuntu 18.04 LTS on VirtualMachine 6.1 on MacBook Pro
HW: Xilinx Vivado/Vitis 2020.2
SW: Petalinux 2020.2Import I2S IP from ADI
Download ADI Xilinx reference IP library from Github repository, then make axi_i2s_adi as following;
% cd hdl-master/library/axi_i2s_adi
% export ADI_IGNORE_VERSION_CHECK=1
% makeIP repository
Start Vivado, Go “Setting -> IP -> repository” then “Add” axi_i2s_adi directory.
Top design
For the FPGA block design, I have referenced several articles below, especially the first article in “ADI Engineer Zone” which includes a PDF top-design schematic.
- Add a small RTL module to control the MUTE pin by the SW on the Zybo board.
- To exactly generate the 12.288MHz audio source clock, two sets of Clock Wizards were configured, one for 50M to 100M and the other for 100M to 12.288MHz clock which feeds into the I2S module and MCLK of SSM2603.
SSM2603 interface and PIN configuration
Bitstream generation
Click “Generate Bitstream” at the bottom on the left panel.
XSA file generation
Then generate “<file name>.xsa” file for VITIS/Petalinux by “File” -> “Export” -> “Export Hardware” and should click the “include bitstream” button.
Sanity check of the FPGA HW platform
Start Vitis, then “File”-> “New”-> “Platform project” with “<file name>.xsa” which is exported by Vivado. “File”-> “New”-> “Application project” with the generated platform then confirm the “Hello World” function.
